1. Field of the Invention
The present disclosure herein relates to an etch proximity correction method, and more particularly, to a method of etch proximity correction for correcting a layout using an etch bias value and a method of creating a photomask layout using the same.
2. Description of the Related Art
With the development of micro-photolithography technology, a scale reduction of an integrated circuit is accelerating further. Thus, a pattern transferred onto a wafer may have a size less than a wavelength of an exposed beam. Accordingly, an optical proximity correction (OPC) for correcting diffraction and interference of light is recognized as being necessary to form a fine pattern having further accuracy and reliability. As fine patterns are adjacent to each other together with the OPC process, requirements of etch proximity correction for minimizing etch effects are being increased.